Silicon quantum dot spin qubits show great promise as a platform for scalable quantum computing due to their sub-μm² on-chip footprint and CMOS-VLSI compatible architecture. Though single-shot spin state readout has been demonstrated using rf-SET charge sensors and dispersive gate reflectometry, both methods rely on off-chip macroscopic electrical resonators. Current designs based on superconducting spiral inductors are large, exceeding 10⁴ μm², suffer from parasitic capacitance and will be limited by cross-chip interconnect scalability. Methods for compact, CMOS-compatible and monolithically integrated spin state readout are highly sought after.

This project investigates a number of novel techniques to achieve this, including:

• On-chip CMOS-compatible capacitively transduced silicon nanomechanical resonators in place of electrical LC resonators, including options for mechanical parametric amplification
• High kinetic inductance thin superconducting films to reduce the inductor footprint, and their epitaxial growth on silicon
• Direct capacitor-bridge measurement of quantum capacitance
• Monolithic co-integration of the above with Cryo-CMOS amplification