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Novel Methods for Compact Readout of Silicon CMOS Quantum Dot Spin Qubits

Quantum computing has the potential to solve problems that are intractable using today’s classical computers, such as simulation of complex systems or large global optimisation problems. Important applications range from discovery of new medicines and functional materials to cryptography and data science. Such algorithms will require millions of quantum bits (qubits) to operate, making scalability a key consideration.

Student

Laurence Cochrane

Supervisor

Dr M. Fernando Gonzalez-Zalba (Hitachi Cambridge Laboratory)
Professor Ashwin Seshia (Nanoscience Centre, Department of Engineering) 

Collaborators/Sponsors

Hitachi Cambridge Laboratory

Silicon quantum dot spin qubits show great promise as a platform for scalable quantum computing due to their sub-μm2 on-chip footprint and CMOS-VLSI compatible architecture. Though single-shot spin state readout has been demonstrated using rf-SET charge sensors and dispersive gate reflectometry, both methods rely on off-chip macroscopic electrical resonators. Current designs based on superconducting spiral inductors are large, exceeding 104 μm2, suffer from parasitic capacitance and will be limited by cross-chip interconnect scalability. Methods for compact, CMOS-compatible and monolithically integrated spin state readout are highly sought after.

This project investigates a number of novel techniques to achieve this, including:

  • On-chip CMOS-compatible capacitively transduced silicon nanomechanical resonators in place of electrical LC resonators, including options for mechanical parametric amplification
  • High kinetic inductance thin superconducting films to reduce the inductor footprint, and their epitaxial growth on silicon
  • Direct capacitor-bridge measurement of quantum capacitance
  • Monolithic co-integration of the above with Cryo-CMOS amplification
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